The present application relates to a non-destructive method to determine crystal defects in a heteroepitaxial semiconductor material layer that is formed on a surface of a semiconductor substrate.
Characterizing wafer and epitaxy defectivity is a fundamental step in fabricating working semiconductor devices and circuits. It is cost paramount not to waste resources building LSI or VLSI circuits on substrates which will not be high yielding. On silicon and silicon epitaxy, numerous etching methods are employed to ensure only the highest quality, lowest defect density substrates. Also, processing steps are available so that if the processing has an issue, the substrate could be scrapped and costs (both from processing (i.e., bandwidth) and yield loss) could be recovered. With heteroepitaxial semiconductor materials such as III-V compound semiconductors and germanium formed on a Si substrate, the prior art etching methods do not work. In one embodiment, a heteroepitaxial semiconductor material is a semiconductor material that is formed by epitaxy on a surface of an underlying semiconductor material, wherein the underlying semiconductor material has a lattice constant that differs from the lattice constant of the epitaxially grown semiconductor material. GaAs grown on a Si substrate is one example.
The current process to completely understand and characterize defect types in substrates or heteroepitaxial semiconductor materials is by using Plan-view transmission electron microscopy (PV-TEM). PV-TEM can be used to measure defect densities down to approximately 106 to 105 defects per square centimeter. Because of the small imaging area, however, lower defect densities cannot be measured reliably by PV-TEM. Moreover, PV-TEM is destructive and cannot be employed as an in-line process control metrology.
In view of the above, there is a need to provide a non-destructive method to determine crystal defects in heteroepitaxial semiconductor materials.